Orla McCoy

UPM Community Engagement Manager

Based in Oxford, UK

Qualcomm; IRDS; Yield enhancement;

Drivers for Defect Control: 3D Heterogenous Integration

UPM spoke with Mustafa Badaroğlu, principal engineer and architect at Qualcomm and chair of the More Moore IRDS global chapter.

On April 7th, Mustafa Badaroğlu spoke about some of these drivers at our UPM Community Event. Watch the event recording here.

Four key trends drive yield enhancement and defect control in semiconductor manufacturing: 
  1. Chip reliability is becoming more important: Safety-critical applications – such as chips for automotives, Industrial Internet of Things (IIoT) and manufacturing control via artificial intelligence, – are in high demand. Defect control is paramount to avoiding chip malfunctions. 
  2. Particle sizes are shrinking: With device scaling reducing chip dimensions, the size of a critical killer defect decreases, making defect detection more difficult. 
  3. Supply chain bottlenecks persist: The global chip shortage makes maintaining chip yield even more critical. 
  4. 3D heterogeneous integration is gaining traction: This trend means that process steps are increasing exponentially, wafer monitoring is becoming more challenging, and defects are more detrimental to production. 

“All these things together demonstrate the importance of ultrapure water for the final product,” Mustafa Badaroğlu explained to UPM. “Ultrapure water is the last line of defense before each next process step and the chip assembly process, as the last step is cleaning wafers with water to remove any residue.” 

3D heterogeneous integration poses a relatively new challenge for ultrapure water production and defect control. 3D heterogeneous integration is the vertical stacking of different die types, such as memory and logic technologies, or different substrate materials. In comparison, monolithic integration (also known as 2D integration) uses a single wafer type and stacks chip technologies horizontally. 

The first generation of 3D scaling exists now in 2022. The IRDS More Moore 2021 update expressed that 3D integration is already happening today, and fine-pitch and 3D VLSI integration will be necessary beyond 2028, but significant reductions in defectivity are required to maximize adoptability. As such, facilities are starting to be built with these considerations in mind. 
Why is 3D heterogenous integration on the technology roadmap? 
Stacking dies vertically allows for shorter interconnections for electrical signals between circuits, therefore leading to better energy efficiency and faster digital transitions. The first generation of 3D integration is solving an important problem for computation, because the memory technology must be very close to the Central Processing Unit (CPU) die.  

Stacking dies vertically is also very important for scaling, especially when combining memory and logic in heterogeneous integration. It is undesirable to integrate different chip types without 3D stacking, as the circuit boards would become very large.   

Heterogeneous integration allows chipmakers to mix and match different ratios of chip technologies for various applications. For example, a data center product would require more memory and less communication capability compared to a consumer product. Other applications for 3D heterogenous integration require the stacking of different substrate materials together for certain products. For example, advanced sensor technology for 6G applications may require gallium arsenide and silicon. 

Finally, 3D heterogenous integration has the potential to ease time-to-market pressures faced by the industry. Foundries are not able to develop all chip types together simultaneously, but by mixing different chip technologies to create different applications, there is continual product output. 
Why does 3D integration have implications for yield? 
Yield of the final product may be reduced when manufacturing technologies reliant on 3D integration, because any flawed chips within the circuit will render the entire circuit defective.  

In addition, 3D heterogeneous integration raises overall process complexity, as more steps are required before chip stacking, and in wafer handling, thinning and metrology. The mask count will increase sequentially, and the probability of failure in each mask step is multiplied. For example, when combining memory and logic technologies, the mask count may be the sum of these two, and as such, there is significant potential for yield to drop. Therefore, the risk that defects will affect yield is higher when using 3D heterogeneous integration. 

These challenges are exacerbated by the lack of metrology for sub-nanometer particles. There are far greater inspection requirements at each step of the process when bringing different die types together.