For the dimensional scaling and performance enhancement of upcoming semiconductor devices, metal wire lines and space minimization are required. However, due to the technical limitation of mask locational alignment accuracy, wiring layer has short circuits and semiconductor performance deteriorates. To prevent short circuit by the misalignment, metal recess technology with etch back metal layer as atomic scale to fill dielectrics and create allowable gap length is required. Furthermore, wire metal has been changed to make interconnect line resistance lower from copper (Cu) to cobalt (Co) and molybdenum (Mo), new wet solutions which are optimize for each is demanded